(vhdl-reset-active-high, vhdl-clock-rising-edge): Improve previous doc

fixes.

diff --git a/lisp/progmodes/vhdl-mode.el b/lisp/progmodes/vhdl-mode.el
index b8399bfafb05a4cc7cfbe0a5a60ec3860f6bf5d4..60c3e1c314477c9740cf4ce35c8e46aed749ad64 100644 (file)
--- a/lisp/progmodes/vhdl-mode.el
+++ b/lisp/progmodes/vhdl-mode.el
@@ -1023,13 +1023,13 @@ NOTE: Activate the new setting in a VHDL buffer by using the menu entry
 
 (defcustom vhdl-reset-active-high nil
   "*Non-nil means reset in sequential processes is active high.
-nil means active low."
+Otherwise, reset is active low."
   :type 'boolean
   :group 'vhdl-sequential-process)
 
 (defcustom vhdl-clock-rising-edge t
   "*Non-nil means rising edge of clock triggers sequential processes.
-nil means falling edge."
+Otherwise, falling edge triggers."
   :type 'boolean
   :group 'vhdl-sequential-process)